1. Field of the Invention
This invention relates to the operation of microprocessors and associated memories.
2. Prior Art
It is known to operate microprocessors in conjunction with associated memories. A microprocessor, or CPU, requests information from the memory. In a typical normal read mode, one data byte or word at a time is obtained from the memory address by the microprocessor. In a typical burst read mode, it is known to obtain more than one data byte or word from multiple memory addresses for the microprocessor. Typically, this requires at least one dedicated burst pin from the microprocessor. Such specialized hardware adds cost and complexity to the semiconductor devices. It would be desirable to overcome and eliminate this problem. These are some of the problems this invention overcomes.
Current burst-mode memories need to interface with dedicated CPU burst signals to support data bursting. These burst signals increase memory chip pin count and logic complexity, thus increasing cost. The purpose of this invention is to show that burst-mode memories can be designed without using dedicated signals to control bursting functions.
Most microprocessors support memory bursting which allows a fast read and/or write of data/instructions over the bus. The advantage of using burst in a computer application is that it eliminates clock cycles between data beats, improving memory access performance. Prior art microprocessors that support a burst-mode require external burst-mode memory to have dedicated control signals to communicate with the CPU during the burst transfer.
For memory read operations using a prior art method for a burst read, the address phase begins when the desired memory address provided by the CPU is latched on the address bus, which occurs when the memory device is activated by a chip enable signal (see FIGS. 2 and 4).
The data phase follows the address phase by at least zero wait states depending on CPU-type and system clock frequency. For prior art Method 1 (FIGS. 1 and 2), the burst transfer begins when the memory receives a dedicated control signal (BURST) from the CPU indicating that the next operation will be a burst transfer. The burst transfer terminates when the memory receives another dedicated control signal (BDIP) which indicates that the next subsequent data byte or word is the last data of the burst transfer. For prior art Method 2 (FIGS. 3 and 4), the burst transfer begins while the chip enable (CE) is activated by alternating odd and even addresses using dedicated control signals (A1 and ADV). The burst transfer terminates when the chip enable is deactivated and/or alternating the control signals terminates.
A computer application can have a 512K byte memory device assembly in a predetermined package. The device has dedicated burst control pins (BURST and BDIP) signals to interface with a CPU to control a burst-mode for reading instructions. If a memory design engineer needs to expand the application's memory to 2M bytes, the memory designer will require two additional address pins. Assuming no pins are available with the predetermined package, the design engineer would require the next larger size package, to add the additional two address pins required for the memory expansion. This would leave a certain number of nonfunctional pins available adding unnecessary cost and complexity to the memory device. It would be desirable to design the memory to use an existing (CE and OE) signal combination to control the burst-mode. The engineer could then remove the dedicated burst control circuitry and make available two extra pins for expanding memory to 2M bytes without adding cost and complexity to the memory design. These are some of the problems this invention overcomes.